The present invention generally relates to an image compression processing apparatus for compressing and displaying image signals denoting an image having a 4:3 aspect ratio on an image display apparatus having a 16:9 aspect ratio.
In recent years, image display apparatuses having a 16:9 aspect ratio and a high-definition receiver have been developed to obtain more realistic television images. However, the more conventional and still existing image signals denoting an image having a 4:3 aspect ratio must be displayed on such apparatuses. Various image compression processing devices are used for this purpose. That is, if original signals denoting a 4:3 image (for example, a circle) are displayed as is on a display apparatus having a 16:9 aspect ratio, the displayed image is expanded in the horizontal direction (to become, for example, an oval as shown in FIG. 1).
An example of the conventional image compression processing apparatus will be described hereinafter with reference to the drawings.
FIG. 1 shows a display image in which an original image signal for an image having a 4:3 aspect ratio is displayed as is on a display apparatus having a 16:9 aspect ratio. FIG. 2 is a block diagram of the conventional image compression processing apparatus. FIG. 3 shows a compression waveform chart thereof. FIG. 4 shows a display image when the image signal of the 4:3 aspect ratio has been compressed and displayed.
In FIG. 2, reference numeral 1 is an A/D converter for converting input signals into digital signals. Reference numeral 2 is a demodulation circuit for image demodulating the output signals of the A/D converter 1. Reference numeral 3 is a synchronous circuit for outputting horizontal pulses at a timing in accordance with clock signal pulses. Reference numeral 4 is a compression circuit for compressing the output signals of the demodulation circuit 2 in a horizontal direction in accordance with the horizontal pulses. Reference numeral 19 is a mask level generating circuit for generating mask levels. Reference numeral 20 is a switching circuit for selectively outputting the output signals of the compression circuit 4 and the mask levels of the mask level generating circuit 19 according to the horizontal pulses output by the synchronous circuit 3. Reference numeral 6 is a D/A converter for converting the output signals of the switching circuit 20 into analog signals.
The operation of the image compression circuit shown in FIG. 2 will be described hereinafter.
The inputted image signals are converted from analog signals to digital signals according to a clock, which is locked in phase to bursts, in an A/D converter 1. The converted digital signals are demodulated in the demodulation circuit 2 so that the demodulation signals A are outputted. The digital signals are also synchronously processed in a synchronous circuit 3 so as to output horizontal pulses D at a timing of a clock signal. In a compression circuit 4, the demodulation signals A, such as those shown in FIG. 3(a), are compressed in a horizontal direction to output compression signals B, such as those shown in FIG. 3(b). Mask levels generated in a mask level generating circuit 19 and the compression signals B are selectively output by a switching circuit 20 according to the horizontal pulses D to obtain output signals C composed of image signals and mask signals. Finally, the signals C are converted into analog signals and outputted by a D/A converter 6 to obtain a display image such as that shown in FIG. 4.
The above described construction suffers a drawback in that the horizontal pulses D are jittered as shown in FIG. 5(a) in a signal without bursts in it and in a signal of a non-standard signal like VCR, which causes jittering in the output signal C at the boundary of the image signal and mask signal as shown in FIG. 5(a), with a problem arising in that the image becomes awkward.